1. Field of the Present Invention
The present invention relates to electronic digital circuitry, and more particularly to devices that enable communication among packaged CMOS logic circuits at very high communication rates and yet at relatively low dynamic power levels by using very low voltage signal swings.
2. Description of the Prior Art
Digital electronic devices and systems typically comprise several integrated circuit packages (ICs) that are interconnected on a printed circuit board assembly. Each of these ICs very often includes whole functional units, not unlike blocks in a block diagram. Digital ICs are ubiquitously supplied with five volts power and have both internal and external signal transitions that approach five volts. Five volt transistor-transistor logic (TTL) has been superseded by complementary metal-oxide-semiconductor (CMOS) logic, which also is typically operated at five volts. The CMOS logic draws far less power under static conditions, compared to TTL, but can draw much higher power under dynamic (switching) conditions because the logic must charge and discharge various stray capacitances and has very short transition times.
Advancements in CMOS fabrication processes have recently enabled the design of very high speed, very complex devices, or "chips", that are capable of clock rates in excess of fifty megahertz (MHz). Prior art CMOS logic systems experience difficulties with such high speeds, especially in inter-chip communication because of the high dynamic power currents involved.
Although the static power consumption of CMOS circuits is generally regarded as being next to insignificant, the dynamic power consumption can be very large and quite troublesome. The high currents principally result from charging and discharging of capacitances associated with internal chip nodes, and with the charging and discharging of load capacitances external to a chip. Both kinds of currents result in power, in the form of heat, being dissipated within the CMOS circuit itself. Manufacturers typically overlook this power consumption phenomenon in their published specifications by describing chip power consumption under test conditions where the outputs are open, or not loaded.
The power dissipated in such logic devices is proportional to the square of the voltage swing charging or discharging a capacitor load. The dynamic power consumption of a node may be expressed as, EQU P.sub.D =CV.sup.2 f, (1)
where P.sub.D is dynamic power in watts, C is the capacitance driven in farads, V is the signal swing in volts, and f is the frequency in Hertz.
Driving individual n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors that constitute CMOS logic also causes power to dissipated. For example, if a node drives a fifty picofarad load with a five volt swing at a fifty MHz rate, equation (1) shows that 62.5 mW of dynamic power will be dissipated. (0.0625=50.times.10.sup.- .multidot.5.sup.2 .multidot.50.times.10.sup.6.) A typical internal node drives between 0.01 picofarad and 0.1 picofarad, but many thousands of internal nodes are usually involved and can add up to fifty picofarads, or more. Large chips can consume several watts of internal dynamic power when operated at high frequencies. For chips that have many output driver circuits, each driving fifty picofarads or more, external dynamic power consumption can also easily be several watts. For example, with eighty output drivers, each switching at twenty-five MHz and driving fifty picofarads, and each swinging five volts, the external power dissipated may be as much as 2.5 watts. This power must be dissipated in the output buffers, which typically comprise a relatively small percentage of the total chip area, and can therefore cause destructive overheating.
There is an industry trend developing towards lower supply voltages of 3.3 volts, rather than the more typical 5.0 volts. Such lower voltages allow more reliable short channel length transistors. CMOS circuits using 3.3 volt supplies may have a nominal 3.3 volt signal swing, and therefore has the side-effect of reducing the dynamic power consumption to 43%, according to equation (1). Although this is a significant power dissipation reduction, large chips can nevertheless still consume several watts of dynamic power.
The present invention reduces dynamic power consumption in CMOS devices by over two orders of magnitude.
Strip line circuit board techniques are called for when signaling at high speed between chips separated by more than approximately eight to ten inches. A terminating resistor network is also required at the receiving end of each signal. The termination network typically comprises two resistors, one connected between a signal line and a ground reference, and the other connected between the signal line and a supply voltage. Each resistor is typically one hundred ohms.
High speed CMOS design does not typically permit the use of such low value terminating resistors because of the high static currents that result. Such currents would cause the typical CMOS device to operate outside its safe operating area. The power consumed in a resistor is proportional to the square of the voltage across the resistor and inversely proportional to the resistor's value. Algebraically expressed, this is, EQU P.sub.R =V.sup.2 /R, (2)
where P.sub.R is the resistive power consumption in watts, V is the signal swing in volts, and R is the terminating resistor values in ohms. For example, if one signal line is terminated with two 100 ohm resistors, and the signal swing is 3.3 volts, then P.sub.R will equal 109 mW, for just one line.
The maximum clock rate is severely limited with CMOS logic by not being able to include proper termination, for example in a long main system bus in a personal computer operating at eight to ten MHz. Only the shorter local buses are able to operate at the much higher clock rates now possible with microprocessors and cache memories.
Several outputs from different chips often share one signal line in a bus arrangement, with only one chip at a time driving the line. The other chips float their outputs. When not being floated, such outputs express very low sink and/or source driving impedances, e.g., approximately five ohms. It is therefore important that a system be designed to guarantee that no two outputs can drive a common signal line in different directions at the same time. Such bus contentions would otherwise cause catastrophic currents that could easily destroy one or more of the drivers involved. In system development this can occur accidentally, before the protective logic is in place.
Very often two inter-communicating CMOS chips reside on different circuit boards which each have a separate power supply. However, the input/output (I/O) lines are common. If one such board is powered up before the other, the I/O lines of the CMOS circuit on the powered down board should preferably be allowed to float, e.g., present a high impedance. Many commercially available CMOS circuits do not include this protection
Very thin gate oxides of less than one hundred Angstroms are desirable in some devices and the newer semiconductor processes have made this practical, and therefore more common. But with such thin gate oxides, it is very difficult to provide adequate electrostatic discharge (ESD) protection, because the thin oxide barrier is so easily breached.